(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to integrate the formation of a shallow junction N channel metal oxide semiconductor field effect transistor (NMOS) device with the fabrication of other type devices, without damaging a shallow source/drain region of the NMOS device.
(2) Description of Prior Art
For performance enhancement as well as for fabrication cost reductions several different type devices are being incorporated in a single semiconductor chip. For example complimentary metal oxide semiconductor (CMOS) devices comprised with both NMOS as well as P channel metal oxide semiconductor (PMOS), devices, can be formed in an integrated process sequence that also allows the formation of an electro-static discharge (ESD) device to be realized. The increased communication between the devices, all located on the same semiconductor chip, results in less wiring and thus decreased resistance and increased performance when compared to counterpart configurations wherein all devices are not on the same semiconductor chip necessitating additional resistive interconnects. In addition fabrication costs are reduced via sharing of specific process steps during the fabrication of the devices.
The ability to obtain desired device characteristics for a specific device, such as an NMOS device used for logic or memory applications, can be influenced by the process sequence chosen for the fabrication of the various devices. For example an NMOS device to be used for logic applications can be designed as a narrow channel length device with a shallow source/drain region. To obtain a shallow source/drain region a low energy ion implantation procedure is employed placing N type dopants near the surface of a semiconductor substrate. If after the NMOS source/drain implantation step other process steps are employed for attainment of other type devices, a portion of the NMOS source/drain dopants located near the surface of the semiconductor substrate can be damaged or removed. This invention will teach a process sequence for the fabrication of several type devices on the same semiconductor chip featuring a source/drain region of an NMOS type device formed after specific process steps for the other type have already been performed. In addition specific process conditions employed after formation of the NMOS source/drain region are altered to reduce the risk of damage or removal of a portion of the already formed NMOS source/drain region. Prior art such as Alvis et al, in U.S. Pat. No. 6,455,385 B1, as well as Doris et al, in U.S. Pat. No. 6,509,221 B1, have described methods of forming CMOS devices as well as optimizing source/drain implantation conditions. However none of the prior art describe the novel process sequence and process steps featured in the present invention allowing the fabrication of a shallow source/drain NMOS device to be integrated with the fabrication of other device types such as a PMOS, a P type I/O and an ESD device.